`timescale 1ns / 1ns

module multi_sel (
    input [7:0] d,
    input clk,
    input rst,
    output reg input_grant,
    output reg [10:0] out
);

    reg [1:0] stat;
    reg [7:0] mul;

    initial begin
        stat <= 0;
        out <= 0;
        input_grant <= 0;
    end

    always @(posedge clk) begin
        input_grant <= (rst != 0 && stat == 0);
        if (rst != 0) begin
            case (stat)
                0: begin
                    mul <= d;
                    out <= d;
                end

                1: begin
                    out <= mul * 3;
                end

                2: begin
                    out <= mul * 7;
                end

                3: begin
                    out <= mul * 8;
                end
            endcase
            stat <= stat + 1;
        end else begin
            out <= 0;
            stat <= 0;
        end
    end

endmodule
